The present invention relates to a digital phase-locked loop for generating a clock signal with the aid of a digitally controlled oscillator (DCO), the clock signal having a defined phase and frequency relationship with a reference clock signal.
The use of analog phase-locked loops (PLLs) is known for generating frequencies which are synchronized with a specific reference frequency. An analog phase-locked loop of this type is disclosed for example in the document F. M. Gardner, “Charge-Pump Phase-Locked Loops”, IEEE Trans. Comm. Vol. 28, pp. 1849-1858, November 1980. This analog phase-locked loop comprises a phase/frequency detector (PFD), which compares the output clock of a voltage-controlled oscillator (VCO) with a reference clock and generates as output signal voltage pulses which contain the information of the phase and frequency difference between the output clock of the voltage-controlled oscillator and the reference clock. The voltage pulses are fed to a charge pump which converts the voltage pulses into corresponding current pulses, these current pulses, for their part, being integrated by a first- or higher-order transimpedance loop filter. Finally, the voltage-controlled oscillator is driven by the output signal of the loop filter in order to set its output clock accordingly. A divider can be arranged in the feedback path between the voltage-controlled oscillator and the phase/frequency detector so that the output clock of the voltage-controlled oscillator divided by a factor N is fed to the phase/frequency detector, where N may be an arbitrary positive number. In the adjusted state of the phase-locked loop, the output frequency of the voltage-controlled oscillator thus corresponds to N times the reference frequency.
If a high frequency resolution with little jitter is demanded, the use of a digitally controlled oscillator (DCO) is advantageous. In this respect, various phase-locked loop architectures have been proposed, the charge pumps and loop filters always having been realized with analog components heretofore.
Thus, by way of example, the document J. Chiang, H. Chen, “A 3.3 all digital phase locked loop with small DCO hardware and fast phase lock”, Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, ISCAS '98, Vol. 1, discloses a digital phase-locked loop wherein, instead of the analog phase/frequency detector, a digital phase detector and a digital frequency detector provided separately therefrom are used. The complexity of the overall system is increased as a result. Moreover, the minimum resolution is generally poorer when using digital phase or frequency detectors than when using analog phase or frequency detectors. Furthermore, this document proposes using a control logic of the digitally controlled oscillator which is connected between the digital phase and frequency detectors and the digitally controlled oscillator. Said control logic performs specific control sequences which can be generalized only with considerable effort if at all, so that the digital phase-locked loop described in this document is not suitable for different applications.
U.S. Pat. No. 5,162,746 A also discloses a digital phase-locked loop wherein a digital phase detector is used in combination with an up/down counter and the output signal of the up/down counter is fed via an appropriately configured decoder to a digitally controlled oscillator for the purpose of correspondingly setting its output clock.
A further digital phase-locked loop is described in the document M. Izumikawa, M. Yamashina, “Compact realization of Phase-Locked loop using digital control”, IEICE Trans. Electron., Vol. E80-C, No. 4, April 1997, wherein, instead of a digitally controlled oscillator, an analog, voltage-controlled oscillator is used whose output clock is compared with a reference clock by a numerical phase detector. The digital control signal generated by the numerical phase detector is fed via a digital loop filter to a digital/analog converter in order to convert the digital control values into corresponding analog control values for the voltage-controlled oscillator. In this case, the number of digital control values corresponds to the frequency resolution of this phase-locked loop.
The previously proposed architectures for a phase-locked loop with a digitally controlled oscillator make it more difficult to effect a stability analysis of the phase-locked loop, or even make said analysis impossible, since the transfer function of the loop filter respectively used and hence the phase and gain stability limits of the phase-locked loop can be varied only with considerable effort, if at all, by the developer. Thus, the loop filter transfer function best suited to the respectively desired application cannot be chosen freely.